Serializer/deserializer apparatus with loopback configuration and methods thereof

ABSTRACT

The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer are directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.

CROSS-REFERENCES TO RELATED APPLICATIONS

This patent application claims priority to and is a continuation of U.S.Nonprovisional patent application Ser. No. 13/802,620, filed Mar. 13,2013, which claims priority to U.S. Provisional Patent Application No.61/641,400, filed May 2, 2012, entitled “Loop-back in SerDes”, all ofwhich are incorporated by reference herein for all purposes.

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH AND DEVELOPMENT

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REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAMLISTING APPENDIX SUBMITTED ON A COMPACT DISK

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BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits.

A Serializer/Deserializer (“SerDes”) is a pair of functional blockscommonly used in high speed communications to compensate for limitedinput/output. These blocks convert data between serial data and parallelinterfaces in each direction. The term “SerDes” generically refers tointerfaces used in various technologies and applications. Typically, aSerDes device has a loopback function, which useful for error checkingand debugging, among other things. There have been conventionaltechniques and systems for providing loopback functions.

Unfortunately, existing loopback techniques in SerDes have beeninadequate. It is therefore desirable to have new and improved systemsand techniques for loopback in SerDes, as described below.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits. In a specificembodiment, high frequency signals from an equalizer are directlyconnected to a first pair of inputs of a sense amplifier. The senseamplifier also has a second pair of inputs, which can be selectivelycoupled to output signals from a DAC or high frequency loopback signals.There are other embodiments as well.

According to an embodiment, the present invention provides an integratedcircuit device. The device includes an equalizer configured to output afirst input voltage and a second input voltage. First input voltage andthe second voltage can be a differential pair. The first input voltagecarries serial data at a frequency of at least 1 GHz. The second inputvoltage carrying serial data at a frequency of at least 1 GHz. Thedevice also includes a digital to analog converter configured to outputa first DAC signal and a second DAC signal. The first DAC signal and thesecond DAC signals are characterized by a frequency of less than 0.5GHz. The device additionally includes a loopback driver being configuredto output a first loopback signal and a second loopback signal. Thefirst loopback signal and the second loopback signal are characterizedby a frequency of at least 1 GHz. The device additionally includes afirst switch coupled to the first loopback signal. The first switchcomprising a first filter. The device also includes a second switchcoupled to the second loopback signal. The second switch includes asecond filter. The device additionally includes a sense amplifier havingfirst input coupled to the first input voltage, a second input coupledto the second input voltage, a third input coupled to the first loopbacksignal through the first switch and the first DAC signal, a fourth inputcoupled to the second loopback signal through the second switch and thesecond DAC signal. The integrated circuit device is configured tooperate in a data mode and a loopback mode. In data mode, the senseamplifier is configured to receive at least the first input voltage andthe first DAC signal, and the first switch is turned off. In loopbackmode, the sense amplifier is configured to receive at least the loopbacksignal, and the first switch is turn on.

According to another embodiment, the present invention provides anintegrated circuit that includes an equalizer configured to output afirst input voltage carrying serial data at a frequency of at least 1GHz. The device also includes a digital to analog converter configuredto output a first DAC signal characterized by a frequency of less than0.5 GHz. The device additionally includes a loopback driver configuredto output a first loopback signal. The first loopback signal ischaracterized by a frequency of at least 1 GHz. The device also includesa first switch coupled to the first loopback signal. The first switchincludes a first filter. The device additionally includes a senseamplifier having first input coupled to the first input voltage and asecond input coupled to the first loopback signal through the firstswitch and the first DAC signal. The integrated circuit device isconfigured to operate in a data mode and a loopback mode. In data mode,the sense amplifier is configured to receive at least the first inputvoltage and the first DAC signal, the first switch being turned off. Inloopback mode, the sense amplifier is configured to receive at least theloopback signal, and the first switch is turn on.

According to yet another embodiment, the present invention provides aSerDes apparatus. The apparatus includes a transmitting circuit and areceiving circuit. The receiving circuit including an equalizerconfigured to output a first input voltage and a second input voltage.The first input voltage carries serial data at a frequency of at least 1GHz. The second input voltage carries serial data at a frequency of atleast 1 GHz. The receiving circuit also includes a digital to analogconverter configured to output a first DAC signal and a second DACsignal. The first DAC signal and the second DAC signals arecharacterized by a frequency of less than 0.5 GHz. The receiving circuitadditionally includes a loopback driver configured receiving a firstloopback signal from the transmitting circuit and to output the firstloopback signal and a second loopback signal. The receiving circuitfurther includes a first switch coupled to the first loopback signal.The first switch includes a low frequency filtering capacitor. Thereceiving circuit also includes a second switch coupled to the secondloopback signal, which also has low frequency filtering capacitor. Thereceiving circuit additionally includes a sense amplifier having firstinput coupled to the first input voltage, a second input coupled to thesecond input voltage, a third input coupled to the first loopback signalthrough the first switch and the first DAC signal, a fourth inputcoupled to the second loopback signal through the second switch and thesecond DAC signal. The SerDes apparatus is configured to operate in adata mode and a loopback mode. In data mode, the sense amplifier isconfigured to receive at least the first input voltage and the first DACsignal, and the first switch is turned off. In loopback mode, the senseamplifier is configured to receive at least the loopback signal, and thefirst switch is turn on.

It is to be appreciated that embodiments of the present inventionprovides numerous advantages. The embodiments of the present inventionprovides techniques and methods that use an offset correction circuitthat is already in existence to couple a loopback signal back to areceiver, thereby preventing additional loss of bandwidth due to theloopback signal path. In addition, embodiments according to the presentinvention can be implemented with existing devices and systems. Thereare other benefits as well.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified diagram illustrating a SerDes apparatus accordingto an embodiment of the invention.

FIG. 2 is a simplified diagram illustrating a conventional SerDesloopback structure.

FIG. 3 is a simplified diagram illustrating a SerDes structure accordingto an embodiment of the present invention.

FIG. 4 is a simplified diagram illustrating a SerDes loopback structureaccording to an embodiment of the present invention.

FIG. 5 is a simplified diagram illustrating a sense amplifier accordingto an embodiment of the present invention.

FIG. 6 is a simplified diagram of a DAC according to an embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits. In a specificembodiment, high frequency signals from an equalizer are directlyconnected to a first pair of inputs of a sense amplifier. The senseamplifier also has a second pair of inputs, which can be selectivelycoupled to output signals from a DAC or high frequency loopback signals.There are other embodiments as well.

As explained above, SerDes are used for many applications. Most SerDestransceivers require an internal loopback feature whereby data is fedfrom the transmitter to the receiver without physically leaving thetransceiver itself. There are reasons for this requirement. First,loopback feature is needed for testing. For example, production test isperformed “at-speed” (e.g., high speed at 28 Gb/s), which is notfeasible with pattern based tests. In addition, loopback feature isoften needed for in-system diagnostics for customers.

For good performance, the loopback process is to be performed as closeto the output line-driver as possible (e.g., as proscribed in the IEEE802.3 standard requirement and also to maximize test coverage).

Adding loopback to a receiver normally involves using multiplexers toisolate the receiver input from the outside world and to couple thetransmitter output directly to the receiver. However, the multiplexerscan add capacitance and/or resistance to the high-bandwidth nodes of thereceiver. This degrades link performance by reducing the receiverbandwidth.

In addition, high bandwidth receiver circuits often require smallgeometry CMOS processes and small device sizes. These circuits tend tohave high inherent offsets that need correcting. Therefore, it is to beappreciated the embodiments of the present invention provides techniquesand methods that use an offset correction circuit that is already inexistence to couple a loopback signal back to a receiver, therebypreventing additional loss of bandwidth due to the loopback signal path.

In various embodiments, the offset correction inputs can receive alow-pass filtered, fixed signal from a DAC which directly corrects forreceiver offsets when in normal operating mode, or a loopback signalfrom the transmitter when in loopback mode. For example, low-passfiltering capacitors can be used in a high-pass mode to AC couple theloop-back signal onto the receiver circuitry as required. When inloopback mode the offset correction is inoperative, but the loopbackmode does not represent a highly stressed condition for the datareceiver. The detailed description is provided below.

The following description is presented to enable one of ordinary skillin the art to make and use the invention and to incorporate it in thecontext of particular applications. Various modifications, as well as avariety of uses in different applications will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to a wide range of embodiments. Thus, the present inventionis not intended to be limited to the embodiments presented, but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

In the following detailed description, numerous specific details are setforth in order to provide a more thorough understanding of the presentinvention. However, it will be apparent to one skilled in the art thatthe present invention may be practiced without necessarily being limitedto these specific details. In other instances, well-known structures anddevices are shown in block diagram form, rather than in detail, in orderto avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which arefiled concurrently with this specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference. All the featuresdisclosed in this specification, (including any accompanying claims,abstract, and drawings) may be replaced by alternative features servingthe same, equivalent or similar purpose, unless expressly statedotherwise. Thus, unless expressly stated otherwise, each featuredisclosed is one example only of a generic series of equivalent orsimilar features.

Furthermore, any element in a claim that does not explicitly state“means for” performing a specified function, or “step for” performing aspecific function, is not to be interpreted as a “means” or “step”clause as specified in 35 U.S.C. Section 112, Paragraph 6. Inparticular, the use of “step of or “act of in the Claims herein is notintended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom,forward, reverse, clockwise and counter clockwise have been used forconvenience purposes only and are not intended to imply any particularfixed direction. Instead, they are used to reflect relative locationsand/or directions between various portions of an object.

FIG. 1 is a simplified diagram illustrating a SerDes apparatus accordingto an embodiment of the invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications. As shown in FIG. 1, the SerDes 100 includes an RX(receiving) functional block 102 and a TX (transmitting) function block101. For example, the TX function block 101 drives the loopback signalsthat is processed by the RX functional block 102.

FIG. 2 is a simplified diagram illustrating a conventional SerDesloopback structure. As shown in FIG. 2, the circuit comprises amultiplexer 203 that is used to select between output from the equalizer201 and output from the loopback driver 202. The output from theequalizer 201 is data transferred during normal operation of the SerDes.The output from the loopback driver 202 is loopback data from the TXblock (not shown) of the SerDes that is typically used for debugging ordiagnostics. Signals from both the equalizer 201 and the loopback driverare high frequency signals (e.g., 28 GHz). The sense amplifier 204 isconfigured to selectively receive signal from either the equalizer 201or the loopback driver 202. For example, in main data mode, the outputfrom the equalizer 201 is selected; in loopback mode, the output fromthe loopback driver 202 is selected. The multiplexer 203 is used toselect output from the equalizer 201 or the loopback driver 202.

As explained above, the multiplexer 203 is used to isolate the receiverinput from the outside world (i.e., data from the equalizer 201) and tocouple the transmitter output directly to the receiver (i.e., data fromthe loopback driver 202). The multiplexer 203, when configured as a partof the SerDes, typically add capacitance and/or resistance tohigh-bandwidth nodes of the receiver of the SerDes, thereby degradinglink performance and reducing the receiver bandwidth. In addition, themultiplexer 203 often takes up too much valuable circuit area. Highbandwidth receiver circuits often require small geometry CMOS processesand small device sizes. Multiplexers, on the other hand, tend to havehigh inherent offsets that need correcting. Therefore, it is to beappreciated that the multiplexer component is removed according toembodiments of the present invention.

FIG. 3 is a simplified diagram illustrating a SerDes structure accordingto an embodiment of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications. As shown in FIG. 3, the loopback section and themultiplexer are removed.

FIG. 4 is a simplified diagram illustrating a SerDes loopback structureaccording to an embodiment of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. As an example, variouscomponents of the circuit 400 are a part of the RX block in FIG. 1. Asshown in FIG. 4, the output of equalizer 403 is directly provided to thesense amplifier 402. For example, the output of the equalizer 403includes receiver input from the outside world. According to variousembodiments, the outputs of the equalizer 403 Vinp and Vinn are receivedas a differential pair. The loopback driver 205 is configured to driveloopback signals Lpdata_p and Lpdata_n. For example, the loopbackssignals Lpdata_p and Lpdata_n constitute a differential pair. In variousembodiments, loopback drivers are implemented with CMOS drivers, but itis to be understood that other drivers are possible as well. The outputsignals from both the equalizer 403 and the loopback driver 405 are highfrequency data signals. For example, the output signals can be 28 GHz.

The digital-to-analog converter (DAC) 404 is configured to provideconvert digital signals to analog signals, and output the analogsignals. In various embodiments, the DAC 404 provides reference signalpair Vrefp and Vrefn. The outputs of the DAC 404, Vrefp and Vrefn, areprovided to the sense amplifier 402. For example, Vrefp and Vrefn areused for offset correction. The offset correction inputs of the senseamplifier 402 can receive a low-pass filtered, fixed signal from the DAC404 which directly corrects for receiver offsets when in normaloperating mode, or a loopback signal from the transmitter when inloopback mode. The outputs of the DAC 404 are at a much lower frequencythan the outputs of the equalizer 403 and loopback driver 405.

The DAC 404 is coupled to the loopback driver 405 through switches andcapacitors. More specifically, the Vrefp output is coupled to theloopback driver 405 through the capacitor C2 and switch 407; the Vrefnoutput is coupled to the loopback driver 405 through the capacitor C1and switch 406. The capacitor and switch pairs are configured to drivethe loopback inputs. More specifically, the capacitors C1 and C2function as low-pass filtering. The capacitances of C1 and C2 arerelated to the filter functions. For example, capacitors C1 and C2 areused to filter the dynamic (switching) change in the DAC 404 outputvoltage. In various embodiments, capacitors C1 and C2 have a capacitanceof about 1 pF to about 10 pF. For example, the capacitors C1 and C2 canbe used in a high-pass mode to AC couple a loopback signal onto thereceiver circuitry as required. The switches 406 and 407 are provided toensure that loopback signals work up to DC. Additionally, the switches406 and 407 determine whether loopback signals pass through, dependingon whether in common data mode or loopback mode. In various embodiments,the switches 406 and 407 are implemented with transmission gates, butother components may be used as well.

The sense amplifier 402 is configured to receive signals from theequalizer 403 at a common data mode, and to receive signals from theloopback driver 405 at a loopback mode. The output of the senseamplifier 402 is provided to the de-multiplexer 401. The operation andan exemplary sense amplifier is illustrated in FIG. 5 and describedbelow. In various embodiments, the de-multiplexer 401 is configured toconvert serial data to parallel data.

The circuit 400 in FIG. 4 operates in common data mode and loopbackmode. At common data mode, the sense amplifier 402 is configured toreceive and process signals from the equalizer 403 and the DAC 404. Thecapacitors C1 and C2 configured to provide filtering. The switches 406and 407 are off, and loopback signals from the loopback drier 405 is notprovided to the sense amplifier 402.

At loopback mode, the sense amplifier 402 is configured to receive andprocess signals from the loopback driver 405. The DAC 404 is on. Thecapacitors C1 and C2 are used to drive the loopback inputs. The switches406 and 407 used to ensure that the loopback works up to DC. Accordingto an embodiment, the equalizer 403 sets the common mode inputs to theVinp/Vinn pins during loopback mode. In various embodiments, when inloopback mode, offset correction is inoperative.

FIG. 5 is a simplified diagram illustrating a sense amplifier accordingto an embodiment of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications. As shown in FIG. 5, a sense amplifier 500 receivesinputs Vinp and Vinn, which can be from the loopback driver in loopbackmode or from the equalizer in common data mode. The Vrefp and Vrefn arereference offsets, which can be received from the DAC. The senseamplifier receives clock signals that drive the input signals.

FIG. 6 is a simplified diagram of a DAC according to an embodiment ofthe present invention. This diagram is merely an example, which shouldnot unduly limit the scope of the claims. One of ordinary skill in theart would recognize many variations, alternatives, and modifications. Asshown in FIG. 6, the DAC 600 is coupled to capacitors C1 and C2. Forexample, the capacitors C1 and C2 are low-pass filtering capacitors.

While the above is a full description of the specific embodiments,various modifications, alternative constructions and equivalents may beused. Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A method for operating an integrated circuitdevice, the method comprising: outputting a first input voltage and asecond input voltage using an equalizer, the first input voltagecarrying serial data at a frequency of at least 1 GHz, the second inputvoltage carrying serial data at a frequency of at least 1 GHz;outputting a first DAC signal and a second DAC signal using a digital toanalog converter, the first DAC signal and the second DAC signals beingcharacterized by a frequency of less than 0.5 GHz; outputting a firstloopback signal and a second loopback signal using a loopback driver,the first loopback signal and the second loopback signal beingcharacterized by a frequency of at least 1 GHz, the first loopbacksignal coupled to a first switch, the first switch comprising a firstfilter, the second loopback signal coupled to a second switch, thesecond switch comprising a second filter; and receiving a signal at asense amplifier, the sense amplifier having a first input coupled to thefirst input voltage, a second input coupled to the second input voltage,a third input coupled to the first loopback signal through the firstswitch and the first DAC signal, a fourth input coupled to the secondloopback signal through the second switch and the second DAC signal;whereupon the equalizer, the digital to analog converter, the loopbackdriver, and the sense amplifier are configured on the integrated circuitdevice.
 2. The method of claim 1 wherein the first input voltage and thesecond voltage are a differential pair.
 3. The method of claim 1 furthercomprising a de-multiplexer coupled to an output of the sense amplifier.4. The method of claim 1 wherein the first reference signal ischaracterized by a frequency of at least 28 GHz.
 5. The method of claim1 wherein: the integrated circuit device is configured to operate in adata mode and a loopback mode; in data mode, the sense amplifier isconfigured to receive at least the first input voltage and the first DACsignal, the first switch being turned off; in loopback mode, the senseamplifier is configured to receive at least the loopback signal, thefirst switch being turn on.
 6. The method of claim 1 wherein the firstswitch comprises a transmission gate.
 7. The method of claim 1 whereinthe first filter comprises a first capacitor, the first capacitor ischaracterized by a capacitance of about 1 pF to 10 pF.
 8. The method ofclaim 1 wherein the first filter is a low-pass filtering capacitor. 9.The method of claim 1 wherein the first switch comprises a transmissiongate configured in parallel to the first filter.
 10. The method of claim1 wherein the signal received by the sense amplifier comprising a firstclock signal and a second clock signal.
 11. The method of claim 1 thesense amplifier is configured to compare the first input voltage to thefirst loopback signal.
 12. The method of claim 1 wherein the DACcomprises two 8-bit converters.
 13. A method for transferringcommunication information using an integrated circuit device, the methodcomprising: outputting a first input voltage carrying serial data at afrequency of at least 1 GHz using an equalizer; outputting a first DACsignal characterized by a frequency of less than 0.5 GHz using a digitalto analog converter; outputting using a loopback driver, a firstloopback signal, the first loopback signal being characterized by afrequency of at least 1 GHz, the first loopback signal being coupled toa first switch coupled to the first loopback signal, the first switchcomprising a first filter; and receiving a signal at a sense amplifier,the sense amplifier having a first input coupled to the first inputvoltage and a second input coupled to the first loopback signal throughthe first switch and the first DAC signal; wherein the equalizer,converter, loopback driver, and sense amplifier are configured on theintegrated circuit device; and wherein: the integrated circuit device isconfigured to operate in a data mode and a loopback mode; in data mode,the sense amplifier is configured to receive at least the first inputvoltage and the first DAC signal, the first switch being turned off. 14.The method of claim 13 wherein the first filter comprises a low-passfiltering capacitor.
 15. The method of claim 13 further comprising clockcoupled to the sense amplifier.
 16. The method of claim 13 furthercomprising a de-multiplexer.
 17. The method of claim 13 wherein theequalizer is directly couple to the sense amplifier.
 18. The method ofclaim 13 further comprising a serial to parallel converter coupled tothe sense amplifier.
 19. The method of claim 13 further wherein thefirst loopback signal is received from a transmitter.
 20. A method ofusing a SerDes apparatus, the method comprising: providing the SerDesapparatus, the apparatus comprising a transmitting circuit; a receivingcircuit, the receiving circuit comprising: an equalizer configured tooutput a first input voltage and a second input voltage, the first inputvoltage carrying serial data at a frequency of at least 1 GHz, thesecond input voltage carrying serial data at a frequency of at least 1GHz; a digital to analog converter configured to output a first DACsignal and a second DAC signal, the first DAC signal and the second DACsignals being characterized by a frequency of less than 0.5 GHz; aloopback driver being configured receiving a first loopback signal fromthe transmitting circuit and to output the first loopback signal and asecond loopback signal; a first switch coupled to the first loopbacksignal, the first switch comprising a first filter; a second switchcoupled to the second loopback signal, the second switch comprising asecond filter; and a sense amplifier having first input coupled to thefirst input voltage, a second input coupled to the second input voltage,a third input coupled to the first loopback signal through the firstswitch and the first DAC signal, a fourth input coupled to the secondloopback signal through the second switch and the second DAC signal; andusing the SerDes apparatus.